DocumentCode
1665169
Title
Mapping of DSP algorithms on the MONTIUM architecture
Author
Heysters, Paul M. ; Smit, Gerard J M
Author_Institution
Dept. of Electr. Eng. Mater. & Comput. Sci., Twente Univ., Enschede, Netherlands
fYear
2003
Abstract
In battery operated mobile devices there is a growing need for flexible high-performance architectures due to the limited amount of available energy and the increasing demand of processing power. Course grained reconfigurable architectures could be the key to more energy-efficient, yet programmable systems. In this paper a course-grained reconfigurable architecture, called MONTIUM, is presented. Several mappings of commonly used digital signal processing algorithms are shown to demonstrate the flexibility of this architecture.
Keywords
digital signal processing chips; parallel algorithms; parallel architectures; reconfigurable architectures; system-on-chip; DSP algorithm mapping; MONTIUM architecture; battery operated mobile devices; course-grained reconfigurable architecture; digital signal processing algorithms; flexible high-performance architectures; programmable systems; Computer architecture; Digital signal processing; Energy efficiency; Hardware; Kernel; Reconfigurable architectures; Registers; Signal processing algorithms; Tiles; VLIW;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel and Distributed Processing Symposium, 2003. Proceedings. International
ISSN
1530-2075
Print_ISBN
0-7695-1926-1
Type
conf
DOI
10.1109/IPDPS.2003.1213333
Filename
1213333
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