DocumentCode :
1665217
Title :
Loop dissevering: a technique for temporally partitioning loops in dynamically reconfigurable computing platforms
Author :
Cardoso, João M P
Author_Institution :
Fac. of Sci. & Technol., Univ. do Algarve, Faro, Portugal
fYear :
2003
Abstract :
This paper presents a technique, called loop dissevering, for temporally partitioning any type of loop presented in programming languages. The technique can be used in the presence of complex loops that oversize the physically available hardware resources. Unlike loop fission or distribution, the technique can be applied to all types of loops and it is not constrained by loop dependences. Thus, the technique guarantees the compilation of complex loops that otherwise cannot be mapped to the target reconfigurable computing architecture. Moreover, the technique only needs to communicate scalar variables between temporal partitions (configurations) and does not need auxiliary array variables used for scalar expansion when applying loop distribution. We show the results of applying the technique when compiling C programs to the PACT eXtreme Processing Platform (XPP) and to a hypothetical version with faster switching between contexts. We show that the technique leads to implementations using fewer resources and might lead to performance improvements when it is possible to overlap some of the execution stages (e.g., fetch, configure, and compute). As performance is concerned, the technique is most efficient and the reconfiguration time is fast.
Keywords :
C language; parallelising compilers; program control structures; reconfigurable architectures; software performance evaluation; C programs; PACT eXtreme Processing Platform; XPP; compilation; complex loops; dynamically reconfigurable computing platforms; loop dissevering; performance improvements; programming languages; reconfigurable computing architecture; scalar variables; temporal partitions; Availability; Computer applications; Computer architecture; Computer languages; Context; Field programmable gate arrays; Hardware; Programmable logic arrays; Programmable logic devices; Reconfigurable architectures;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel and Distributed Processing Symposium, 2003. Proceedings. International
ISSN :
1530-2075
Print_ISBN :
0-7695-1926-1
Type :
conf
DOI :
10.1109/IPDPS.2003.1213335
Filename :
1213335
Link To Document :
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