Logic synthesis for pass-transistor design

New logic CMOS families using pass-transistor circuit techniques have recently been proposed with the objective of improving speed and power consumption. The double pass-transistor logic, developed by Hitachi in 1993 has proven that in 0.25 μm CMOS technology, DPL full adder is as fast as that of CPL. In this work, a method for synthesis of pass-transistor logic has been developed. It has been shown by simulation that in terms of speed this family outperforms standard CMOS design. The logic developed using described techniques is also advantageous in terms of power as compared to static CMOS. The new logic presented in this paper represents an improvements over DPL, made by elimination of the redundant branches and rearrangement of signals