DocumentCode
1665780
Title
Improved clock buffer with high PSRR for SC circuit applications
Author
VanPeteghem, Peter M.
Author_Institution
Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
fYear
1989
Firstpage
1705
Abstract
The PSRR (power-supply rejection ratio) in switched-capacitor (SC) circuits is dominated by clock feedthrough. As a result PSRR figures are typically too low for high-performance signal processing. A novel high-PSRR CMOS clock buffer, which effectively blocks this power supply (PS) noise coupling path, is presented. The circuit is a significant improvement over an earlier circuit proposed by the author (IEEE Int. Symp. on Circ. & Syst., p.68-71, May 1987), having with a simulated PSRR of over 40 dB
Keywords
CMOS integrated circuits; integrated circuit technology; switched capacitor networks; SC circuit; clock buffer; clock feedthrough; high PSRR; high-PSRR CMOS clock buffer; high-performance signal processing; power-supply rejection ratio; Analog integrated circuits; Circuit noise; Clocks; Coupling circuits; Cutoff frequency; Digital integrated circuits; Integrated circuit noise; Power supplies; Switches; Switching circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1989., IEEE International Symposium on
Conference_Location
Portland, OR
Type
conf
DOI
10.1109/ISCAS.1989.100693
Filename
100693
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