A 175µW 100MHz-2GHz inductorless receiver front-end in 65nm CMOS

A digital process, voltage, and temperature (PVT) calibration loop for a Frequency-to-Voltage converter (FVC) is presented. The FVC needs a precisely controlled delay element, but delay in CMOS is highly dependent on the PVT condition making it necessary to calibrate the delay line. The system is designed to calibrate against an external reference frequency which is already present in the intended application. This is advantageous, as it is not necessary to generate additional bandgap or other reference on chip. Results from transistor level simulations using a 90 nm CMOS process are presented, showing good regulation across PVT corners and ability to track changes in the PVT condition. The calibration loop is digital and therefore a good fit for CMOS technology.