On CMOS scaling and A/D-converter performance

Author

Jonsson, Bengt E.

Author_Institution

ADMS Design AB, Delsbo, Sweden

fYear

2010

Firstpage

1

Lastpage

4

Abstract

The influence of CMOS scaling on A/D-converter performance is investigated by observing the entire body of experimental CMOS ADCs reported in IEEE journals and conferences central to the field from 1976 to 2010. Based on the near-exhaustive set of scientific data, empirically observed scaling trends are derived for performance in terms of noisefloor, speed and resolution, as well as for power efficiency expressed by two commonly used figures-of-merit. The trends are used to estimate limits on the achievable ADC performance in nanometer CMOS technologies, with implications for LTE and WCDMA infrastructure applications particularly highlighted.

Keywords

CMOS integrated circuits; Long Term Evolution; analogue-digital conversion; code division multiple access; A/D-converter performance; CMOS scaling; LTE; WCDMA infrastructure; figure-of-merit; nanometer CMOS technologies; power efficiency; scaling trends; scientific data; CMOS integrated circuits; CMOS technology; Floors; Power dissipation; Signal to noise ratio; Trajectory; ADC; Analog-digital conversion; CMOS; LTE; SoC; Telecommunication; VLSI technology; WCDMA;

fLanguage

English

Publisher

ieee

Conference_Titel

NORCHIP, 2010

Conference_Location

Tampere

Print_ISBN

978-1-4244-8972-5

Electronic_ISBN

978-1-4244-8971-8

Type

conf

DOI

10.1109/NORCHIP.2010.5669483

Filename

5669483