Title :
A 14.2mW 2.55-to-3GHz cascaded PLL with reference injection, 800MHz delta-sigma modulator and 255fsrms integrated jitter in 0.13μm CMOS
Author :
Park, Dongmin ; Cho, SeongHwan
Author_Institution :
KAIST, Daejeon, South Korea
Abstract :
Fractional-N PLLs [1-3] are widely used due to their fine frequency resolution. However, their phase noise performance is typically worse than the integer-N [4, 5, 6] counterpart due to the quantization noise of the delta-sigma modulator (DSM). In this paper, we propose a low-noise fractional-N PLL that achieves best-case figure-of-merit (FOM) of -240.3dB, rms jitter of 255fsrms and worst-case fractional spur of -53.9dBc by using an 800MHz reference generated from a low-noise reference-injected integer-N PLL.
Keywords :
CMOS integrated circuits; delta-sigma modulation; phase locked loops; CMOS; cascaded PLL; delta-sigma modulator; figure-of-merit; fine frequency resolution; frequency 2.55 GHz to 3 GHz; frequency 800 MHz; integrated jitter; low noise reference-injected integer-N PLL; phase noise performance; power 14.2 mW; quantization noise; reference injection; size 0.13 mum; worst-case fractional spur; Frequency measurement; Jitter; Noise measurement; Phase locked loops; Phase noise; Semiconductor device measurement;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4673-0376-7
DOI :
10.1109/ISSCC.2012.6177038
