Title :
Voltage handling capability and termination techniques of silicon power semiconductor devices
Author_Institution :
Lab. d´´Autom. et d´´Anal. des Syst., CNRS, Toulouse, France
fDate :
6/23/1905 12:00:00 AM
Abstract :
Firstly, the author revisits the methodology used to calculate the avalanche breakdown voltage of power semiconductor devices. He shows that the classical formulations using Van Oversraeten ionisation coefficient can lead to an underestimation of about 45% regarding the voltage handling capability. Next a review is presented of the major termination techniques used today in microelectronics, mainly planar compatible. Their principle is shown and some general considerations about their drawbacks and advantages given. A comparison is given regarding some criteria such as their static and dynamic efficiency, the space used, the voltage range covered, the ease of design and the technological feasibility
Keywords :
avalanche breakdown; elemental semiconductors; impact ionisation; isolation technology; power semiconductor devices; semiconductor device breakdown; semiconductor device metallisation; silicon; Si; Si power semiconductor devices; avalanche breakdown voltage; dynamic efficiency; field plate; ionisation coefficient; microelectronics; planar compatible type; static efficiency; termination techniques; voltage handling capability; voltage range; Avalanche breakdown; Breakdown voltage; Charge carrier processes; Impact ionization; Microelectronics; Power semiconductor devices; Semiconductor devices; Silicon; Space technology; Termination of employment;
Conference_Titel :
Bipolar/BiCMOS Circuits and Technology Meeting, Proceedings of the 2001
Conference_Location :
Minneapolis, MN
Print_ISBN :
0-7803-7019-8
DOI :
10.1109/BIPOL.2001.957885
