Title :
Powering networks on chips
Author :
Benini, Luca ; De Micheli, Giovanni
Author_Institution :
DEIS, Bologna Univ., Italy
fDate :
6/23/1905 12:00:00 AM
Abstract :
We consider systems on chips that can be designed and produced in five to ten years from today, with gate lengths in the range 50-100 nm. We address the distinguishing features of a design methodology that aims at achieving reliable designs under the limitations of the interconnect technology. Specifically, we consider energy consumption reduction, under guaranteed quality of service, as a main objective in system design.
Keywords :
microprocessor chips; multiprocessor interconnection networks; power consumption; quality of service; system buses; 50 to 100 nm; application layer; data-link layer; interconnections on chip; low-energy design; network layer; networks on chips; physical layer; software layers; systems on chips; transport layer; Clocks; Design methodology; Energy consumption; Energy efficiency; Permission; Power system interconnection; Power system reliability; Quality of service; System-on-a-chip; Wires;
Conference_Titel :
System Synthesis, 2001. Proceedings. The 14th International Symposium on
Print_ISBN :
1-58113-418-5
DOI :
10.1109/ISSS.2001.156528
