Cache-efficient memory layout of aggregate data structures

Author

Panda, Preeti Ranjan ; Semeria, Luc ; De Micheli, Giovanni

Author_Institution

Synopsys Inc., Mountain View, CA, USA

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

101

Lastpage

106

Abstract

We describe an important memory optimization that arises in the presence of aggregate data structures such as arrays and structs in a C/C++ based system design methodology. We present an algorithm for determining an optimized memory layout of such data. Our implementation consists of a pointer analysis and resolution phase, followed by memory layout optimization. Experiments on typical applications from the DSP domain result in up to 44% improvement in memory performance.

Keywords

cache storage; data structures; digital signal processing chips; memory architecture; program control structures; storage management; C/C++ based system design methodology; DSP domain; aggregate data structures; cache-efficient memory layout; memory layout optimization; memory optimization; memory performance; optimized memory layout; pointer analysis; pointer resolution phase; structs; Aggregates; Algorithm design and analysis; Application software; Computer languages; Data structures; Design methodology; Design optimization; Embedded software; Hardware; Integrated circuit synthesis;

fLanguage

English

Publisher

ieee

Conference_Titel

System Synthesis, 2001. Proceedings. The 14th International Symposium on

Print_ISBN

1-58113-418-5

Type

conf

DOI

10.1109/ISSS.2001.156540

Filename

957921