Title :
An FPGA implementation of a flexible, parallel image processing architecture suitable for embedded vision systems
Author :
McBader, Stephanie ; Lee, Peter
Author_Institution :
NeuriCam S.p.A, Trento, Italy
Abstract :
This paper describes the design of a programmable parallel architecture that is to be used for signal pre-processing in intelligent embedded vision systems. The architecture has been implemented and tested using a Celoxica RC1000 prototyping platform with a Xilinx XCY2000E FPGA. The system operates at a clock rate of 50 MHz and can perform pre-processing functions such as filtering, correlation and transformation on an image of 256x256 pixels at up to 667 frames/s.
Keywords :
computer vision; embedded systems; field programmable gate arrays; image processing; parallel architectures; Celoxica RC1000 prototyping platform; FPGA implementation; Xilinx XCY2000E FPGA; embedded vision systems; parallel image processing architecture; programmable parallel architecture; Clocks; Field programmable gate arrays; Filtering; Image processing; Intelligent systems; Machine vision; Parallel architectures; Prototypes; Signal design; Testing;
Conference_Titel :
Parallel and Distributed Processing Symposium, 2003. Proceedings. International
Print_ISBN :
0-7695-1926-1
DOI :
10.1109/IPDPS.2003.1213415
