• DocumentCode
    166722
  • Title

    ESD device performance analysis in a 14nm FinFET SOI CMOS technology: Fin-based versus planar-based

  • Author

    Li, Junjun ; Gauthier, Robert ; Li, You ; Mishra, Rahul

  • Author_Institution
    IBM Semiconductor Research and Development Center, Essex Junction, VT 05452 USA
  • fYear
    2014
  • fDate
    7-12 Sept. 2014
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    We present ESD device results from a 14nm FinFET SOI CMOS technology. Both fin-based and planar-based approaches are evaluated, with the planar-based diode design achieving 7 times higher failure current per silicon area. Planar-based diodes also show 25% higher failure current when Tsi increases by 40%.
  • Keywords
    Electrostatic discharges; FinFETs; Logic gates; Performance evaluation; Semiconductor diodes; Silicon; Substrates;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2014 36th
  • Conference_Location
    Tucson, AZ, USA
  • ISSN
    0739-5159
  • Type

    conf

  • Filename
    6968796
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=166722