Title :
Bitline-capacitance-cancelation sensing scheme with 11ns read latency and maximum read throughput of 2.9GB/s in 65nm embedded flash for automotive
Author :
Jefremow, Mihail ; Kern, Thomas ; Backhausen, Ulrich ; Peters, Christian ; Parzinger, Christoph ; Roll, Christoph ; Kassenetter, Stephan ; Thierold, Stefanie ; Schmitt-Landsiedel, Doris
Author_Institution :
Infineon, Neubiberg, Germany
Abstract :
This paper presents a BL-capacitance-cancelation sensing scheme implemented in a 65nm embedded FLASH technology to overcome the speed limitations of conventional voltage sensing. It is combined with a continuous precharge scheme as described in to increase the robustness of the system supporting the low-swing-sensing phase.
Keywords :
automotive electronics; electric sensing devices; flash memories; automotive; bit rate 2.9 Gbit/s; bitline-capacitance-cancelation sensing scheme; continuous precharge scheme; conventional voltage sensing; embedded flash; low-swing-sensing phase; maximum read throughput; read latency; size 65 nm; time 11 ns; Arrays; Automotive engineering; Capacitance; Electric potential; Microprocessors; Sensors;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4673-0376-7
DOI :
10.1109/ISSCC.2012.6177076
