Title :
Synthesis of configurable linear feedback shifter registers for detecting random-pattern-resistant faults
Author :
Chen, Chien-In Henry
Author_Institution :
Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA
fDate :
6/23/1905 12:00:00 AM
Abstract :
We describe an optimized BIST scheme which has a configurable 2-D LFSR structure. A synthesis procedure for this test generator is presented. Experimental results show that the hardware overhead is considerably reduced compared with 2-D LFSR generators. The experiment result shows that compared with the non-configurable 2-D LFSR, the average number of flip-flops is reduced by 79% for five benchmark circuits. The average number of faults detected by the configurable 2-D LFSR is 9.27% higher than that of the conventional LFSR and 0.57% higher than that of the non-configurable 2-D LFSR.
Keywords :
VLSI; built-in self test; flip-flops; logic testing; shift registers; configurable linear feedback shifter registers; faults detection; flip-flops; hardware overhead; optimized BIST scheme; random-pattern-resistant faults; synthesis procedure; test generator; Benchmark testing; Built-in self-test; Circuit faults; Circuit synthesis; Circuit testing; Electrical fault detection; Fault detection; Feedback; Flip-flops; Hardware;
Conference_Titel :
System Synthesis, 2001. Proceedings. The 14th International Symposium on
Print_ISBN :
1-58113-418-5
DOI :
10.1109/ISSS.2001.156559
