• DocumentCode
    166744
  • Title

    An Update Method for a CAM Emulator Using an LUT Cascade Based on an EVMDD (K)

  • Author

    Nakahara, H. ; Sasao, T. ; Matsuura, Motoharu

  • Author_Institution
    Kagoshima Univ., Kagoshima, Japan
  • fYear
    2014
  • fDate
    19-21 May 2014
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    Core routers perform longest prefix matching (LPM) using content addressable memories (CAMs). With the rapid growth of the Internet, LPM has become the bottleneck in network traffic management. In a previous publication, we have proposed an area-efficient and high-performance CAM emulator using an LUT cascade based on an edge-valued multi-valued decision diagram (EVMDD (k)). In the inter-net, registered vectors must be updated frequently. In this paper, we propose an algorithm to update an LUT cascade. We implemented the proposed algorithm on the ARM processor. Its update time is shorter than the peak update time of the BGP protocol. Experimental results show that, as for the lookup speed per area, our architecture outperforms existing CAM realizations on FPGAs.
  • Keywords
    Internet; access protocols; content-addressable storage; field programmable gate arrays; microprocessor chips; table lookup; ARM processor; BGP protocol; CAM emulator; EVMDD; FPGA; Internet; LPM; LUT cascade; content addressable memories; core routers; edge-valued multivalued decision diagram; longest prefix matching; lookup speed per area; network traffic management; registered vectors; update method; Computer aided manufacturing; Field programmable gate arrays; Indexes; Memory management; Rails; Table lookup; Vectors; BDD; Decision Diagram; LUT cascade; MDD; Multiple Valued Logic; Packet Classification;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Multiple-Valued Logic (ISMVL), 2014 IEEE 44th International Symposium on
  • Conference_Location
    Bremen
  • ISSN
    0195-623X
  • Type

    conf

  • DOI
    10.1109/ISMVL.2014.9
  • Filename
    6844987