FPGA implementation using Renoir tools: application for bit timing logic (BTL) synthesis of controller area network with 100% free error

Author

Abouda, Kamel ; Ducaud, Jerôme ; Henry, Herve ; Aucouturier, J.L.

Author_Institution

Lab. d´´Etude de l´´Integration des Composants et Syst. Electron., Bordeaux I Univ., Talence, France

fYear

1998

fDate

6/20/1905 12:00:00 AM

Firstpage

29

Lastpage

32

Abstract

Logic synthesis using VHDL simplifies considerably logic circuit design. However, when the application requires a few thousand lines of VHDL code, it is very beneficial to use graphic software that can produce the VHDL code. But, it is always necessary to master the VHDL language. In this paper we have studied VHDL generated with three basic processes of the Renoir state machine. An application for designing, synthesizing and implementing a bit timing logic of an ISO normalized controller area network (CAN) is given. It has been tested with 100% free error

Keywords

controller area networks; field programmable gate arrays; finite state machines; hardware description languages; logic CAD; timing; FPGA implementation; ISO normalized controller area network; Renoir state machine; Renoir tools; VHDL; bit timing logic; logic synthesis; Application software; Circuit synthesis; Field programmable gate arrays; Graphics; ISO; Logic circuits; Logic design; Network synthesis; Testing; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, 1998. ICM '98. Proceedings of the Tenth International Conference on

Conference_Location

Monastir

Print_ISBN

0-7803-4969-5

Type

conf

DOI

10.1109/ICM.1998.825560

Filename

825560