Title :
Functional verification with completely self-checking tests
Author :
Zhang, Eugene ; Yogev, Einat
Author_Institution :
Cisco Syst. Inc., USA
Abstract :
Writing thorough testbenches to verify complex systems is becoming increasingly difficult and time-consuming. This paper analyzes existing functional verification methodologies, as well as some fundamental problems of functional verification of complex systems. This paper proposes a more powerful and efficient approach for writing fully self-checking tests, using a transaction-based verification method, and concurrent programming techniques. A generic 32×32 cell-based switch fabric system is used as an example to illustrate this methodology
Keywords :
application specific integrated circuits; asynchronous transfer mode; automatic testing; formal verification; hardware description languages; logic CAD; parallel programming; ASIC; ATM; Vera; Verilog; cell-based switch fabric system; completely self-checking tests; complex systems verification; concurrent programming; functional verification; testbench; time-consuming; transaction-based verification; Application specific integrated circuits; Automatic testing; Clocks; Fabrics; Functional programming; Hardware design languages; Microprocessors; Switches; System testing; Writing;
Conference_Titel :
Verilog HDL Conference, 1997., IEEE International
Conference_Location :
Santa Clare, CA
Print_ISBN :
0-8186-7955-7
DOI :
10.1109/IVC.1997.588525