Early branch prediction circuit for high performance digital signal processors

Author

Farooqui, Aamir A. ; Oklobdzija, Vojin G.

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA

fYear

1998

fDate

6/20/1905 12:00:00 AM

Firstpage

95

Lastpage

98

Abstract

In this paper, design and VLSI implementation of an Early Branch Prediction (EBP) circuit, based on a variation of Carry Look-ahead scheme is presented. The key features of this design are low area, high speed (2[log n/2]+1), and high modularity. This design out performs all the EBP designs presented so far. For 64 bit word length the early branch prediction is obtained in 679 ps as simulated for 0.2 μ technology under typical conditions. Simulation and layout results for 0.2 μ CMOS technology show a 30% increase in speed with 25% decrease in area as compared, to recently published results

Keywords

CMOS digital integrated circuits; VLSI; digital signal processing chips; integrated circuit design; 0.2 micron; 64 bit; CMOS chip; VLSI design; carry look-ahead circuit; digital signal processor; early branch prediction circuit; CMOS technology; Circuits; Computational modeling; Delay; Design engineering; Digital signal processors; Hardware; Logic; Predictive models; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, 1998. ICM '98. Proceedings of the Tenth International Conference on

Conference_Location

Monastir

Print_ISBN

0-7803-4969-5

Type

conf

DOI

10.1109/ICM.1998.825577

Filename

825577