Advantages and challenges of high performance CMOS on SOI

Author

Pelella, M.M. ; Maszara, W. ; Sundararajan, S. ; Sinha, S. ; Wei, A. ; Ju, D. ; En, W. ; Krishnan, S. ; Chan, D. ; Chan, S. ; Yeh, P. ; Lee, Minhung ; Wu, Dalei ; Fuselier, M. ; vanBentum, R. ; Burbach, G. ; Lee, C. ; Hill, G. ; Greenlaw, D. ; Riccobenc,

Author_Institution

Logic Technol. Dev., Adv. Micro Devices Inc., Sunnyvale, CA, USA

fYear

2001

Firstpage

1

Lastpage

4

Abstract

The key performance advantages and challenges of SOI CMOS for ULSI applications are discussed in detail. Included is an insightful analysis comparing the performance benefits of SOI technologies over its bulk-Si counterpart. The hysteretic trends of a floating-body PD/SOI inverter circuit are uniquely characterized using a Teradyne J971 system; and the charge-dump and self-heating effects are shown to be under control using an advanced 0.13 /spl mu/m SOI device technology. Future technology opportunities are described that could provide a viable roadmap of SOI technologies to leverage in the future.

Keywords

CMOS logic circuits; NAND circuits; ULSI; integrated circuit reliability; silicon-on-insulator; technological forecasting; 0.13 micron; DC I-V characteristics; NAND circuits; SOI CMOS; Si-SiO/sub 2/; Teradyne J971 system; ULSI applications; charge-dump effect; charge-dump effects; floating-body inverter circuit; future technology opportunities; high performance; hysteresis; partially depleted SOI; performance advantages; reliability; ring-oscillator propagation delays; self-heating effects; Body regions; CMOS technology; Capacitance; Inverters; MOSFET circuits; Performance analysis; Predictive models; Propagation delay; Temperature; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 2001 IEEE International

Conference_Location

Durango, CO, USA

ISSN

1078-621X

Print_ISBN

0-7803-6739-1

Type

conf

DOI

10.1109/SOIC.2001.957957

Filename

957957