A 1.7mW 11b 250MS/s 2× interleaved fully dynamic pipelined SAR ADC in 40nm digital CMOS

In recent years ADC research has resulted in impressive advances in power efficiency. SAR ADCs have reached energies per conversion step below 10fJ, but only at rather low sampling frequencies [1] or moderate resolution [2]. Wireless receivers for next-generation, higher-bandwidth standards such as LTE-advanced, however, will require much faster ADCs. We present a fully dynamic, two-times interleaved pipelined SAR ADC that achieves 10fJ/conversion-step with 9.5 ENOB at a sampling speed as high as 250MS/s.