• DocumentCode
    166815
  • Title

    An effective ESD program management based on S20.20 plus ESD capability/risk analysis

  • Author

    Yan, K.P. ; Gaertner, R. ; Wong, C.Y.

  • Author_Institution
    Infineon Technol. (Malaysia) Sdn. Bhd., Melaka, Malaysia
  • fYear
    2014
  • fDate
    7-12 Sept. 2014
  • Firstpage
    1
  • Lastpage
    7
  • Abstract
    The semiconductor back end manufacturing process starts from the wafer dicing process and finishes with the final tested product with many processes in between where the ESD protection requirement may vary to a great extent. To have an effective ESD control of the different process steps, an ESD protection concept based on S20.20 alone is not sufficient. The control strategy additionally should be based on ESD process capability/risk analysis. The paper provides a macro overview on how an effective ESD program management is established in a semiconductor manufacturing facility.
  • Keywords
    electrostatic discharge; risk analysis; semiconductor device manufacture; wafer level packaging; ESD capability analysis; ESD program management; ESD protection requirement; ESD risk analysis; S20.20; semiconductor back end manufacturing process; semiconductor manufacturing facility; wafer dicing process; Discharges (electric); Electrostatic discharges; Footwear; Materials; Process control; Sawing; Wires;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2014 36th
  • Conference_Location
    Tucson, AZ
  • ISSN
    0739-5159
  • Type

    conf

  • Filename
    6968845