A 1.0TOPS/W 36-core neocortical computing processor with 2.3Tb/s Kautz NoC for universal visual recognition

Author

Tsai, Chuan-Yung ; Lee, Yu-Ju ; Chen, Chun-Ting ; Chen, Liang-Gee

Author_Institution

Nat. Taiwan Univ., Taipei, Taiwan

fYear

2012

Firstpage

480

Lastpage

482

Abstract

In this paper, an NC processor for power-efficient real-time universal visual recognition is proposed with following features: 1) A grey matter-like homogeneous many-core architecture with event-driven hybrid MIMD execution provides 1.0TOPS/W efficient acceleration for NC operations; 2) A white matter-like Kautz NoC provides 2.3Tb/s throughput, fault/congestion avoidance and redundancy-free multicast with 151Tb/s/W NoC power efficiency, which is 2.7-3.9x higher than previous NoC-based visual recognition processors.

Keywords

image recognition; multiprocessing systems; network-on-chip; parallel processing; 36-core neocortical computing processor; NC processor; NoC power efficiency; event-driven hybrid MIMD execution; fault-congestion avoidance; grey matter-like homogeneous many-core architecture; power-efficient real-time universal visual recognition; redundancy-free multicast; white-matter-like Kautz NoC; Arrays; Feature extraction; Image recognition; Real time systems; Routing; Visualization;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

978-1-4673-0376-7

Type

conf

DOI

10.1109/ISSCC.2012.6177099

Filename

6177099