DocumentCode
1668285
Title
0.11 /spl mu/m fully-depleted SOI CMOS devices with 26 nm silicon layer fabricated by bulk compatible process
Author
Komatsu, H. ; Nakayama, H. ; Koyama, K. ; Matsumoto, K. ; Ohno, T. ; Takeshita, K.
Author_Institution
LSI Technol. Dev. Div., Sony Corp., Atsugi, Japan
fYear
2001
Firstpage
23
Lastpage
24
Abstract
A design for fully-depleted (FD) SOI CMOS devices is proposed. By optimizing halo/extension implantation and a thin CoSi/sub 2/ process, 0.11 /spl mu/m FD devices with a flat roll-off have been fabricated, even with a 26 nm thick Si layer . Using this "bulk compatible" technology, a good inverter switching speed of 14 ps (at V/sub dd/=1.2 V) has been achieved.
Keywords
MOSFET; ion implantation; leakage currents; low-power electronics; semiconductor device measurement; silicon-on-insulator; 0.11 micron; 1.2 V; 14 ps; 26 nm; FD SOI CMOS; Si-CoSi/sub 2/; bulk compatible process fabrication; bulk compatible technology; flat roll-off; fully-depleted SOI CMOS devices; halo/extension implantation; inverter switching speed; thin CoSi/sub 2/ process; Annealing; Dielectric devices; Metallization; Silicon; Very large scale integration; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
SOI Conference, 2001 IEEE International
Conference_Location
Durango, CO, USA
ISSN
1078-621X
Print_ISBN
0-7803-6739-1
Type
conf
DOI
10.1109/SOIC.2001.957966
Filename
957966
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