Enhanced write performance of a 64 Mb phase-change random access memory

Author

Hyung-rok On ; Cho, Beak-Hyung ; Cho, Woo Yeong ; Kang, Sangbeom ; Choi, Byung-Gil ; Kim, Ki-Sung ; Kim, Ki-Sung ; Kim, Du-Eung ; Kwak, Choong-Keun ; Byun, Hyun-Geun ; Jeong, Gi-Tae ; Jeong, Hong-Sik ; Kim, Kinam

Author_Institution

Samsung Electron., Hwasung, South Korea

fYear

2005

Firstpage

48

Abstract

A 1.8 V 64 Mb phase-change RAM with improved write performance is fabricated in a 0.12 μm CMOS technology. The improvement of RESET and SET distributions is based on cell current regulation and multiple step-down pulse generators. The read access time and SET-write time are 68 ns and 180 ns respectively.

Keywords

CMOS memory circuits; phase change materials; pulse generators; random-access storage; 0.12 micron; 1.8 V; 180 ns; 64 Mbit; 68 ns; CMOS; RAM enhanced write performance; RESET distribution; SET distribution; SET-write time; cell current regulation; multiple step-down pulse generators; phase-change random access memory; read access time; CMOS technology; Conductivity; Crystallization; Flash memory; Germanium alloys; Low voltage; Nonvolatile memory; Phase change random access memory; Tellurium; Tin alloys;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

0-7803-8904-2

Type

conf

DOI

10.1109/ISSCC.2005.1493862

Filename

1493862