• DocumentCode
    1668470
  • Title

    A 0.6 to 9.6Gb/s binary backplane transceiver core in 0.13μm CMOS

  • Author

    Krishna, Kannan ; Yokoyama-Martin, David A. ; Wolfer, Skye ; Jones, Chris ; Loikkanen, Mat ; Parker, James ; Segelken, Ross ; Sonntag, Jeff L. ; Stonick, John ; Titus, Steve ; Weinlader, Daniel

  • Author_Institution
    Synopsys, Hillsboro, OR, USA
  • fYear
    2005
  • Firstpage
    64
  • Abstract
    A backplane transceiver core in 0.13 μm dual-gate CMOS, operating at 0.6 to 9.6 Gb/s with an area of 0.56 mm2 and dissipating 150 mW at 6.25 Gb/s, is presented. This core uses a unique adaptive receive equalization strategy, transmit pre-emphasis, and has extensive optional test features including a built-in BER tester and an on-chip receiver sampling scope.
  • Keywords
    CMOS integrated circuits; adaptive equalisers; data communication equipment; transceivers; 0.13 micron; 0.6 to 9.6 Gbit/s; 150 mW; 6.25 Gbit/s; adaptive receive equalization strategy; binary backplane transceiver core; built-in BER tester; dual-gate CMOS; on-chip receiver sampling scope; transmit pre-emphasis; Backplanes; Capacitance; Crosstalk; Decision feedback equalizers; Frequency; Intersymbol interference; Resistors; Switches; Transceivers; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    0-7803-8904-2
  • Type

    conf

  • DOI
    10.1109/ISSCC.2005.1493870
  • Filename
    1493870
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1668470