Architectural frameworks for MPP systems on a chip

Advances in fabrication techniques are now enabling new hybrid CPU/FFPGA computing resources to be integrated onto a single chip. While these new hybrids promise significant performance increases through the customization of massive gate level parallelism, their full potential will not be reached until a suitable computational framework has been developed. We believe that the computational framework should provide a unified model that brings the FPGA and CPU based components under a common programming model for MPP developers. In this paper, we discuss extending the thread programming model to support hybrid CPU and FPGA computational components to allow systems programmers to access the MPP level of parallelism potential of the FPGA, but within a familiar and understood programming model.