A switched capacitors track&hold circuit for subsampling applications

The growing need for dense wireless communication circuits in the frequency range of 900 MHz, has forced IC designers to find alternative receivers to the superheterodyne architecture. Among these alternatives, the direct-conversion by subsampling system should be promising because it offers a high level of integration. However, due to sampling noise and aperture jitter this architecture is certainly restricted to applications which do not need high performance. In this paper a switched capacitor track&hold suitable in a front-end of a subsampling receiver will be described. The circuit has been designed in a 0.6 μm MOS technology. It works under 3.3 V and with a clock frequency of 25 MHz. Simulation results show that the circuit could track a signal as high as 900 MHz