Ultra-thin film fully-depleted SOI CMOS with raised G/S/D device architecture for sub-100 nm applications

Fully-Depleted (FD) Silicon-on-Insulator (SOI) has become very attractive for deep submicron CMOS applications because of its quasi-ideal properties. Scaling FD SOI involves, amongst many other technology parameters, reducing the thickness of the silicon film. However, thinning the SOI film down to 50 nm or below may result in high series resistance or even full consumption of the silicon during the salicidation process. Therefore, a dedicated device architecture is needed like for example the raised gate/source/drain (G/S/D) device architecture. The authors have fabricated FD SOI transistors on top of an ultra-thin silicon film of 30 nm with gate lengths down to 0.1 /spl mu/m. After a short description of the device fabrication, the electrical results on DC and HF performance are presented and discussed.