Title :
Recessed multi-gate SOI MOSFET in deep decananometer regime
Author :
Jvi-Tsong Lin ; Shih-chang Chang ; Kuo-ying Huang ; Yan-Youg Xu ; Ping-Shin Jue
Author_Institution :
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
Abstract :
A recessed multi-gate SOI MOSFET has been presented. Due to the confinement finite volume and strong coupling between the three-wide folded gate and back gate. the electrical field inside the silicon film is smoothed and the carrier mobility is enhanced. Thus. the controllability of the gate is improved so that the ultrashort channel effect/DIBL and ultranarrow width effect are further suppressed. in addition, the higher transconductance with higher integration density. the near ideal subthreshold slope, the postponed single latch breakdown. and the suppressed self-heating effect have been also demonstrated for the recessed multi-gate SOI MOSFET. We believed that if the ultra-thin silicon film, thin BOX and novel material are exploited, the decananometer multi-gate device with good performance can be realized in the nearest future.
Keywords :
CMOS integrated circuits; MOSFET; ULSI; ion implantation; semiconductor device breakdown; silicon-on-insulator; sputter etching; DIBL; Si-SiO/sub 2/; TCAD; ULSI; bipolar snap breakdown; carrier mobility; channel implantation; confinement finite volume; fabrication; gate controllability; higher transconductance; near ideal subthreshold slope; postponed single latch breakdown; reactive ion etching; recessed multigate SOI MOSFET; single latch issue; subthreshold factor; suppressed self-heating effect; thin BOX; three-wide folded gate; ultranarrow width effect; ultrashort channel effect; CMOS process; Etching; FinFETs; MOSFET circuits; Process design; Semiconductor films; Silicidation; Silicon; Transconductance; Transistors;
Conference_Titel :
SOI Conference, 2001 IEEE International
Conference_Location :
Durango, CO, USA
Print_ISBN :
0-7803-6739-1
DOI :
10.1109/SOIC.2001.957978
