DocumentCode
1668763
Title
Measurement of history effect in PD/SOI single-ended CPL circuit
Author
Jenkins, K.A. ; Puri, R. ; Chuang, C.T. ; Pesavento, F.L.
Author_Institution
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fYear
2001
Firstpage
57
Lastpage
58
Abstract
Single-ended complementary pass-transistor logic (CPL), also known as LEAP. has been a popular choice for implementing high-performance arithmetic operations due to its efficiency in device use. The circuit, however, is predicted to exhibit a large history effect when implemented in a partially depleted SOI (PD/SOI) technology. This paper presents direct measurement of its history effect in a 0.18/spl mu/m, 1.5V PD/SOI technology with L/sub eff/ = 0.08 /spl mu/m and t/sub ox/ = 2.3 nm.
Keywords
CMOS integrated circuits; silicon-on-insulator; 0.08 micron; 0.18 micron; 1.5 V; 2.3 nm; PD/SOI single-ended CPL circuit; high-performance arithmetic operations; history effect; single-ended complementary pass-transistor logic; Arithmetic; Delay effects; Frequency; History; Inverters; Logic circuits; Logic devices; MOS devices; Oscilloscopes; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
SOI Conference, 2001 IEEE International
Conference_Location
Durango, CO, USA
ISSN
1078-621X
Print_ISBN
0-7803-6739-1
Type
conf
DOI
10.1109/SOIC.2001.957983
Filename
957983
Link To Document