• DocumentCode
    1668827
  • Title

    Novel 0.8 V true-single-phase-clocking (TSPC) latches using PD-SOI DTMOS techniques for low-voltage CMOS VLSI circuits

  • Author

    Kuo, J.B. ; Tai-Yi Chiang

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
  • fYear
    2001
  • Firstpage
    63
  • Lastpage
    64
  • Abstract
    This paper reports two novel true-single-phase-clocking (TSPC) latches using partially-depleted (PD) SOI CMOS dynamic threshold (DTMOS) techniques for low-voltage CMOS VLSI circuits. Via controlling the body voltage dynamically the 0.8 V split-output PD-SOI TSPC latch using DTMOS techniques shows an 85% reduction in the switching time and less slow clock problems as verified by MEDICI simulation results.
  • Keywords
    CMOS integrated circuits; VLSI; flip-flops; integrated circuit modelling; logic gates; silicon-on-insulator; 0.8 V; 0.8 V true-single-phase-clocking latches; MEDICI simulation; PD-SOI DTMOS techniques; body voltage; low-voltage CMOS VLSI circuits; slow clock problems; switching time; CMOS logic circuits; CMOS technology; Clocks; Latches; Low voltage; MOS devices; Partial discharges; Telephony; Threshold voltage; Voltage control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOI Conference, 2001 IEEE International
  • Conference_Location
    Durango, CO, USA
  • ISSN
    1078-621X
  • Print_ISBN
    0-7803-6739-1
  • Type

    conf

  • DOI
    10.1109/SOIC.2001.957986
  • Filename
    957986
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1668827