5+ GHz CMOS prescaler

Author

Fleming Lam ; Wu, G.

Author_Institution

Peregrine Semicond. Corp., San Diego, CA, USA

fYear

2001

Firstpage

65

Lastpage

66

Abstract

This paper addresses the design of high-performance and low power circuits in SOI technology. In particular, our ultra thin silicon (UTSi/sup (R)/) silicon-on-sapphire (SOS) process has successfully been used to design a working divide-by-2 prescaler which operates in excess of 5 GHz using a 0.5 /spl mu/m process. Measured data will be presented to support simulation results. Based on the performance seen to date using 0.5 /spl mu/m technology, a significantly higher performance is expected in 0.25 /spl mu/m technology and beyond.

Keywords

CMOS logic circuits; high-speed integrated circuits; integrated circuit design; integrated circuit measurement; low-power electronics; prescalers; sapphire; silicon-on-insulator; 0.25 micron; 0.5 micron; 5 GHz; Al/sub 2/O/sub 3/; Al/sub 2/O/sub 3/-Si; CMOS prescaler; SOI; SOS; UTSi; divide-by-2 prescaler; high-performance circuits; low power circuits; ultra thin silicon silicon-on-sapphire; CMOS logic circuits; CMOS technology; Clocks; Delay; Feedback; Packaging; Parasitic capacitance; Predictive models; Silicon; Temperature sensors;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 2001 IEEE International

Conference_Location

Durango, CO, USA

ISSN

1078-621X

Print_ISBN

0-7803-6739-1

Type

conf

DOI

10.1109/SOIC.2001.957987

Filename

957987