Analog design with Verilog-A

Verilog-A is a language to describe analog behavior. It is an extension to the IEEE 1364 Verilog Hardware Description Language (HDL) specification. A complete definition of the Verilog-A hardware description language, as proposed by the analog Technical Subcommittee of Open Verilog International (OVI), can be found in the Verilog-A Language Reference Manual (LRM). An LRM to describe mixed signal, Verilog-AMS, is in development and will be available in 1997. Several Verilog-A prototype simulators are now in development and three are available from commercial CAD tool providers. This paper contains information about Verilog-A, the motivation to develop it, some thoughts on model development, and an example of a Verilog-A module