Title :
Analog design with Verilog-A
Author :
Miller, Ira ; FitzPatrick, Dan ; Aisola, Ramana
Author_Institution :
Motorola Inc., Tempe, AZ, USA
Abstract :
Verilog-A is a language to describe analog behavior. It is an extension to the IEEE 1364 Verilog Hardware Description Language (HDL) specification. A complete definition of the Verilog-A hardware description language, as proposed by the analog Technical Subcommittee of Open Verilog International (OVI), can be found in the Verilog-A Language Reference Manual (LRM). An LRM to describe mixed signal, Verilog-AMS, is in development and will be available in 1997. Several Verilog-A prototype simulators are now in development and three are available from commercial CAD tool providers. This paper contains information about Verilog-A, the motivation to develop it, some thoughts on model development, and an example of a Verilog-A module
Keywords :
IEEE standards; analogue circuits; circuit analysis computing; digital simulation; hardware description languages; logic CAD; CAD tool; IEEE 1364; Language Reference Manual; Open Verilog International; Verilog Hardware Description Language; Verilog-A; analog design; hardware description language; mixed signal Verilog-AMS; model development; prototype simulators; specification; Design methodology; Hardware design languages; Integrated circuit modeling; Manuals; Performance analysis; Signal design; Software libraries; Standards development; TV; Virtual prototyping;
Conference_Titel :
Verilog HDL Conference, 1997., IEEE International
Conference_Location :
Santa Clare, CA
Print_ISBN :
0-8186-7955-7
DOI :
10.1109/IVC.1997.588533
