A novel shallow trench isolation technology using LPCVD MTO/SiN liner in SOI wafer

A novel Shallow Trench Isolation (STI) technology has been proposed for the device fabrication using SOI wafers. The trench sidewall oxidation is replaced with MTO (Medium Temperature Oxide) and Silicon Nitride (SiN) to prevent the SOI bending problem. SiN Liner over MTO scheme showed the additional benefits such as reduced field oxide recess and improved gate oxide quality, Stress Induced Leakage Current (SILC) and Time Zero Dielectric Breakdown (TZDB). We also compared the bonded SOI and SIMOX wafers in terms of the gate oxide quality for the different STI liner schemes.