Reduction of STI/active stress on 0.18 /spl mu/m SOI devices through modification of STI process

Stress from shallow trench isolation was found to cause up to 19% variation in 0.18 /spl mu/m technology SO! devices. Partially depleted SOI devices were fabricated on a 0.18 /spl mu/m technology with 100 nm thick silicon film and 200 nm thick buried oxide. The STI edge parallel to the edge of the gate was found to induce compressive stress on the SOI device. For N-Ch devices. closer proximity of the STI edge resulted in a 18% degradation of the Iona channel transconductance (gm.max). The opposite trend was observed for P-Ch devices. STI stress reduction was achieved by switching the liner oxidation step in the STI formation from before the trench oxide fill to after. The STI stress improvement resulted in 50% reduction of the dependence of the long channel gm.max to the proximity of the STI trench edge. The lower STI stress improved the device variation between different SOI transistor layout geometries.