Title :
Bit-level systolic carry-save array division
Author :
Dawid, Herbert ; Fettweis, Gerhard
Author_Institution :
Aachen Univ. of Technol., Germany
Abstract :
A bit-level systolic carry-save division array that allows bit-level pipelining, just as for carry-save array multipliers, is presented. This architecture leads to very fast, efficient and regular division implementations as needed in digital signal processing (DSP) applications such as speech processing or cryptography. The architecture is very well suited for integer division as well as for the division of normalized fixed-point mantissas used in floating-point number system implementations
Keywords :
digital arithmetic; systolic arrays; DSP; bit-level pipelining; carry-save array multipliers; cryptography; digital signal processing; floating-point number system; integer division; normalized fixed-point mantissas; speech processing; systolic carry-save array division; Computer architecture; Cryptography; Delay; Digital signal processing; Hardware; Iterative algorithms; Pipeline processing; Signal processing algorithms; Speech processing; Very large scale integration;
Conference_Titel :
Global Telecommunications Conference, 1992. Conference Record., GLOBECOM '92. Communication for Global Users., IEEE
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-0608-2
DOI :
10.1109/GLOCOM.1992.276550
