Title :
System level simulation of a SIMD active memory enhanced PC (or, why we don´t want 100% bandwidth utilisation)
Author :
Mangnall, J. ; Quigley, S.
Author_Institution :
Univ. of Birmingham, UK
Abstract :
Merged logic and DRAM "active memory" or processing-in-memory (PIM) devices are widely recognised as a mechanism to avoid the memory wall bottlenecks exhibited by modern computing platforms. As several design efforts are working on commodity DRAM replacement parts, we present a simulation architecture for a SIMD active memory enhanced workstation. Additionally, we show that actually making use of all the available bandwidth presented by a DRAM to on-chip logic will significantly degrade the performance of an interactive multitasking environment. In order to minimise this performance degradation, we present a modified data tiling technique to allow the SIMD array\´s register file to be used as a cache.
Keywords :
DRAM chips; cache storage; integrated injection logic; memory architecture; parallel architectures; performance evaluation; virtual machines; workstations; DRAM; PIM devices; SIMD array; active memory enhanced PC; bandwidth utilisation; cache register file; interactive multitasking environment; memory wall bottlenecks; merged logic; modified data tiling; on-chip logic; performance degradation; processing-in-memory devices; system level simulation; workstation; Bandwidth; Computational modeling; Computer architecture; Degradation; Hardware; Logic devices; Operating systems; Performance analysis; Random access memory; Workstations;
Conference_Titel :
Parallel and Distributed Processing Symposium, 2003. Proceedings. International
Print_ISBN :
0-7695-1926-1
DOI :
10.1109/IPDPS.2003.1213506
