• DocumentCode
    1669256
  • Title

    A low-cell-stress SOI SRAM sensing technique

  • Author

    Kuang, J.B. ; Assaderaghi, F. ; Aipperspach, A.G. ; Christensen, T.A.

  • Author_Institution
    Adv. Server Dev., IBM Corp., Rochester, MN, USA
  • fYear
    2001
  • Firstpage
    95
  • Lastpage
    96
  • Abstract
    In this paper, we present a low-cell-stress latch-type sensing system, which seeks to bias the bit lines low as frequently as possible to relieve voltage stress on the access transistor for improved cell stability and yield while maintaining high performance. This technique is desirable for low-power circuit applications.
  • Keywords
    SRAM chips; elemental semiconductors; silicon; silicon-on-insulator; Si-SiO/sub 2/; access transistor; bit lines; cell stability; high performance; low-cell-stress SOI SRAM sensing technique; low-cell-stress latch-type sensing system; low-power circuit applications; voltage stress; yield; CMOS technology; Circuits; Degradation; Hysteresis; Rails; Random access memory; Silicon; Stability; Topology; Voltage control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOI Conference, 2001 IEEE International
  • Conference_Location
    Durango, CO, USA
  • ISSN
    1078-621X
  • Print_ISBN
    0-7803-6739-1
  • Type

    conf

  • DOI
    10.1109/SOIC.2001.958003
  • Filename
    958003
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1669256