DocumentCode :
16693
Title :
Multichip Embedding Technology Using Fine-Pitch Cu–Cu Interconnections
Author :
Khan, Shoab Ahmed ; Choudhury, Alamgir ; Kumbhat, Nitesh ; Pulugurtha, M.R. ; Sundaram, Venky ; Meyer-Berg, G. ; Tummala, Rao
Author_Institution :
3-D Syst. Packaging Res. Center, Georgia Inst. of Technol., Atlanta, GA, USA
Volume :
3
Issue :
2
fYear :
2013
fDate :
Feb. 2013
Firstpage :
197
Lastpage :
204
Abstract :
Increasing performance and functional density while maintaining low cost is a catalyst for technological progress in the field of packaging. From flip-chip with solder to a hybrid approach of copper and solder, many methods have been created to reach this objective. The 3-D Packaging Research Center at Georgia Tech has been revolutionizing interconnection technology with the multichip embedding chip-last approach, which utilizes ultrathin adhesive-bonded copper bumps to enable ultrafine-pitch chip-to-package interconnections. This technology has been proven to be highly reliable using a low-cost low-temperature direct copper-to-copper bonding approach at 30-μm pitch and ~20-μm standoff height copper-to-copper interconnections. This interconnection method provides a platform for integration with flip-chip packages through its proven ability to work well with different die sizes and thicknesses bonded to the surface of ultrathin organic substrates. The next step in advancing the chip-last approach is to investigate chip embedding at the single-chip and multichip levels. Consequently, this paper focuses on: 1) the design and fabrication of the test vehicle to examine the reliability of the previously demonstrated copper-to-copper interconnections after embedding a thin die in an organic substrate, and 2) assembly process development and reliability data for the interconnections. Specifically, advances in the assembly process include: 1) a novel method to perform chip-last assembly at the panel level leading to a 10-15 times reduction in assembly time per die, and 2) an improved two-step assembly process to achieve simultaneous die embedding and cavity planarization. This embedding technology and its advancements not only allow actives to be embedded in organic substrates but also enables higher functional integration at high-throughput, making chip-last adhesive bonding with low-profile copper-to-copper interconnections a robust chip embedding solution- for the next generation of highly integrated heterogeneous subsystems.
Keywords :
adhesive bonding; assembling; catalysts; chip scale packaging; copper alloys; flip-chip devices; integrated circuit interconnections; solders; 3D packaging research center; Cu-Cu; Georgia Tech; assembly process development; catalyst; cavity planarization; chip-last adhesive bonding; chip-last assembly; copper-to-copper interconnections; die embedding planarization; flip-chip packages; improved two-step assembly process; integrated heterogeneous subsystems; low-cost low-temperature direct copper-to-copper bonding approach; low-profile copper-to-copper interconnections; multichip embedding chip-last approach; multichip embedding technology; panel level; reliability data; robust chip embedding solution; solder; test vehicle design; test vehicle fabrication; ultrafine-pitch chip-to-package interconnections; ultrathin adhesive-bonded copper; ultrathin organic substrates; Assembly; Bonding; Cavity resonators; Reliability; Substrates; Surface treatment; Vehicles; Copper; interconnections; packaging;
fLanguage :
English
Journal_Title :
Components, Packaging and Manufacturing Technology, IEEE Transactions on
Publisher :
ieee
ISSN :
2156-3950
Type :
jour
DOI :
10.1109/TCPMT.2012.2235528
Filename :
6415254
Link To Document :
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