DocumentCode
1669344
Title
Integrated parallel scrambler design for high-speed transmission systems
Author
Lee, Sang H. ; Lee, Pil J.
Author_Institution
Bell Commun. Res., Morristown, NJ, USA
fYear
1988
Firstpage
361
Abstract
A general parallel scrambling procedure based on exact relationships between high-speed and low-speed m -sequences is described. In particular, a novel implementation scheme using only one pure-cycling shift register without any exclusive-OR (XOR) gate in the feedback loop for generating the parallel scrambling sequences is presented. The use of a crosspoint switch in this method makes it applicable to a selectable multiplexing factor, thereby enabling the design of a general-purpose parallel scrambling circuit
Keywords
cryptography; sequential circuits; shift registers; crosspoint switch; feedback loop; high-speed transmission systems; m-sequences; parallel scrambling procedure; pure-cycling shift register; selectable multiplexing factor; Feedback loop; Linear feedback shift registers; Shift registers; Signal generators; Statistics; Switches; Switching circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1988., IEEE International Symposium on
Conference_Location
Espoo
Type
conf
DOI
10.1109/ISCAS.1988.14939
Filename
14939
Link To Document