• DocumentCode
    1669347
  • Title

    Novel circuits to improve SRAM performance in PD/SOI technology

  • Author

    Joshi, R.V. ; Bhavnagarwala, A. ; Hsu, L.L. ; Chuang, C.T. ; Hwang, Wei

  • Author_Institution
    Div. of Res., IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
  • fYear
    2001
  • Firstpage
    99
  • Lastpage
    100
  • Abstract
    A novel circuit technique is proposed to overcome the read disturbance by parasitic bipolar currents in PD/SOI technology. Results show that using the new circuit, larger bitline differentials can be achieved with improvement in performance by more than 18%.
  • Keywords
    SRAM chips; elemental semiconductors; integrated circuit measurement; integrated circuit noise; leakage currents; silicon; silicon-on-insulator; PD/SOI technology; SRAM performance; Si-SiO/sub 2/; bipolar leakage current; bitline differentials; noise; parasitic bipolar current; parasitic bipolar currents; read disturbance; Circuit noise; Clocks; Degradation; Delay; Logic circuits; Logic gates; Microelectronics; Power supplies; Random access memory; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOI Conference, 2001 IEEE International
  • Conference_Location
    Durango, CO, USA
  • ISSN
    1078-621X
  • Print_ISBN
    0-7803-6739-1
  • Type

    conf

  • DOI
    10.1109/SOIC.2001.958005
  • Filename
    958005
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1669347