• DocumentCode
    1669357
  • Title

    A portable mechanism for vectorizing compiled event-driven simulation

  • Author

    Mittra, Swapnajit

  • Author_Institution
    HaL Comput. Syst. Inc., USA
  • fYear
    1997
  • Firstpage
    70
  • Lastpage
    76
  • Abstract
    This paper presents a portable mechanism for vectorization of a hardware description language (HDL) in a multiprocessing environment. Each of the functional modules in the environment is atomized and put in a centralized event queue using the dynamic event scheduling mechanism. However, during the execution phase, the set of events in a particular time instant form, what we call a `rope´ of independent events. Each of the events in a rope is simulated through the creation of an independent thread in the environment. In a multiprocessing operating system (OS) this means, depending on the availability of the processor time-slice, an independent thread created from the same process will run in parallel on different processors without any special input from the program thus ensuring a platform independent portable mechanism. As there is no direct interaction between the program and the kernel of the OS, it is possible to port the code even on a uni-processor machine without any change in the code
  • Keywords
    circuit analysis computing; discrete event simulation; hardware description languages; logic CAD; multiprocessing systems; network operating systems; scheduling; software portability; Verilog; centralized event queue; compiled event-driven simulation; dynamic event scheduling; execution phase; hardware description language; independent events; multiprocessing environment; multiprocessing operating system; platform independent portable mechanism; processor time-slice; uniprocessor machine; vectorization; Computational modeling; Computer simulation; Discrete event simulation; Dynamic scheduling; Hardware design languages; Mathematical model; Operating systems; Portable computers; Processor scheduling; Yarn;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Verilog HDL Conference, 1997., IEEE International
  • Conference_Location
    Santa Clare, CA
  • Print_ISBN
    0-8186-7955-7
  • Type

    conf

  • DOI
    10.1109/IVC.1997.588535
  • Filename
    588535