Assessing circuit level impact of self-heating in 0.13 /spl mu/m SOI CMOS

3D simulations have been performed to study the impact of self-heating in SOI on circuits. Using multiple finger structures we have established bounds on the magnitude of the heat increase and its behavior with device scaling. This allows circuit designers to quickly evaluate temperature variations in real circuits under various operating conditions. for various device sizes and subject to different current density thanks to simple scaling of the presented results. The approach gives a simple and efficient way to take into account self heating in circuit optimization. In addition. contrary to previous studies, we have found that the heat predominantly flows through the buried oxide.