Title :
Mixed 2-4 state simulation with VCS
Author :
Chowdhury, Dibakar Roy
Abstract :
To meet the demand for higher performance, today´s logic simulators are supporting 2 state simulation. Within Chronologic Simulation´s VCS simulation system, we have implemented an elaborate infrastructure to support mixed 2-4 state simulation in Verilog. The paper presents our approach to allow mixed 2-4 state simulation while retaining compliance to Verilog HDL language and its simulation semantics. The key issues that need consideration for mixed 2-4 state simulation are discussed in detail. The results obtained by running VCS regression test suite and OVI regression test suite are summarized
Keywords :
digital simulation; hardware description languages; logic CAD; 2 state simulation; Chronologic Simulation; OVI regression test suite; VCS regression test suite; VCS simulation system; Verilog HDL language; logic simulators; mixed 2-4 state simulation; simulation semantics; Design methodology; Electronic design automation and methodology; Hardware design languages; Logic design; MOS devices; Performance gain; Sections; Signal design; Signal resolution; Testing;
Conference_Titel :
Verilog HDL Conference, 1997., IEEE International
Conference_Location :
Santa Clare, CA
Print_ISBN :
0-8186-7955-7
DOI :
10.1109/IVC.1997.588537
