Title :
Lateral gate-all-around (GAA) poly-Si transistors
Author :
Kalavade, P. ; Saraswat, K.C.
Author_Institution :
Dept. of Electr. Eng., Stanford Univ., CA, USA
Abstract :
High performance near-single grain poly-Si lateral gate-all-around (GAA) MOS transistors have been demonstrated. A high I/sub ON//I/sub OFF/ ratio of 10/sup 8/ and nearly ideal subthreshold slope of 67 mV/dec were achieved. These devices were fabricated using a novel technique for crystallization of a-Si. resulting in substantial improvements in transistor performance as well as uniformity without the use of self-implantation. or any external crystallization seeding agents. The technology is simple, scalable, and CMOS compatible and therefore attractive for 3-D device integration.
Keywords :
CMOS integrated circuits; MOSFET; elemental semiconductors; silicon; silicon-on-insulator; 3D device integration; CMOS compatible system; MOS transistors; SOI; Si; high performance near-single grain transistors; lateral gate-all-around poly-Si transistors; nearly ideal subthreshold slope; uniformity; Annealing; CMOS technology; Computational Intelligence Society; Crystallization; Fabrication; Grain boundaries; MOSFETs; Silicon; Substrates; Wet etching;
Conference_Titel :
SOI Conference, 2001 IEEE International
Conference_Location :
Durango, CO, USA
Print_ISBN :
0-7803-6739-1
DOI :
10.1109/SOIC.2001.958010
