A Quality of Service Network on Chip based on a new priority arbitration mechanism

Multiprocessor system-on-chip (MP-SoC) platforms are emerging as an important trend for SoC design. Network on Chips (NoC) become the preferred on-chip communication platform for current and future SoC architectures. In this paper, we present the design of a new on chip network with Quality-of Service (QoS) support. The proposed routers use new dynamic arbitration architecture with a priority-based scheduler to differentiate between multiple packets with various QoS requirements. A wormhole input queued 2-D mesh router was created to verify the capability of our router. Various parameterized designs were synthesized to provide a comparative study with other implementations in FPGA technology, with different flit size. Finally, a performance study in terms of average latency and throughput of 4×4 mesh 2-D network was conducted to prove the benefit of using the QoS packets and finding the saturation point.