DocumentCode
1669514
Title
A streaming processing unit for a CELL processor
Author
Flachs, B. ; Asano, S. ; Dhong, S.H. ; Hotstee, P. ; Gervais, G. ; Kim, R. ; Le, T. ; Liu, P. ; Leenstra, J. ; Liberty, J. ; Michael, B. ; Oh, H. ; Mueller, S.M. ; Takahashi, O. ; Hatakeyama, A. ; Watanabe, Y. ; Yano, N.
Author_Institution
IBM Corp., Austin, TX, USA
fYear
2005
Firstpage
134
Abstract
The design of a 4-way SIMD streaming data processor emphasizes achievable performance in area and power. Software controls data movement and instruction flow, and improves data bandwidth and pipeline utilization. The micro-architecture minimizes instruction latency and provides fine-grain clock control to reduce power.
Keywords
delays; multimedia communication; parallel architectures; pipeline processing; 4-way SIMD; CELL processor; data bandwidth; data movement; fine-grain clock control; instruction flow; instruction latency minimization; micro-architecture; pipeline utilization; reduced power; streaming data processor; streaming processing unit; Acceleration; Bandwidth; Buffer storage; Computer architecture; Frequency; Logic; Pipelines; Process design; Registers; Streaming media;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
0-7803-8904-2
Type
conf
DOI
10.1109/ISSCC.2005.1493905
Filename
1493905
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