DocumentCode :
1669602
Title :
FPGA correlator architecture using random-pulse data representation
Author :
Al-Dhaher, Abdul ; Petriu, Emil M. ; Dostaler, Marc
Author_Institution :
Sch. of Inf. Technol. & Eng., Ottawa Univ., Ont., Canada
Volume :
2
fYear :
2002
fDate :
6/24/1905 12:00:00 AM
Firstpage :
1061
Abstract :
This paper discusses design issues for the FPGA implementation of parallel, serial-parallel and serial correlator architecture using random-pulse representation.
Keywords :
correlators; field programmable gate arrays; FPGA correlator architecture; parallel architecture; random-pulse data representation; serial architecture; serial-parallel architecture; Analog computers; Arithmetic; Biology computing; Clocks; Computer architecture; Correlators; Field programmable gate arrays; Quantization; Stochastic resonance; Virtual reality;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Instrumentation and Measurement Technology Conference, 2002. IMTC/2002. Proceedings of the 19th IEEE
ISSN :
1091-5281
Print_ISBN :
0-7803-7218-2
Type :
conf
DOI :
10.1109/IMTC.2002.1007102
Filename :
1007102
Link To Document :
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