• DocumentCode
    1669665
  • Title

    Advantages RTL partial scan synthesis

  • Author

    Greene, Bruce S. ; Mourad, Samiha

  • Author_Institution
    Synopsys Inc., USA
  • Volume
    2
  • fYear
    2002
  • fDate
    6/24/1905 12:00:00 AM
  • Firstpage
    1077
  • Abstract
    This paper presents an efficient algorithm for selecting flip-flops for partial scan design. Compared to gate-level techniques, our results indicate that selecting registers on the register-transfer level (RTL) guarantees excellent fault coverage without incurring high hardware overhead.
  • Keywords
    flip-flops; high level synthesis; RTL algorithm; fault coverage; flip-flop; hardware overhead; partial scan synthesis; register selection; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Feedback; Flip-flops; Hardware; Logic testing; Registers; Sequential analysis;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Instrumentation and Measurement Technology Conference, 2002. IMTC/2002. Proceedings of the 19th IEEE
  • ISSN
    1091-5281
  • Print_ISBN
    0-7803-7218-2
  • Type

    conf

  • DOI
    10.1109/IMTC.2002.1007105
  • Filename
    1007105
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1669665