Title :
Advantages RTL partial scan synthesis
Author :
Greene, Bruce S. ; Mourad, Samiha
Author_Institution :
Synopsys Inc., USA
fDate :
6/24/1905 12:00:00 AM
Abstract :
This paper presents an efficient algorithm for selecting flip-flops for partial scan design. Compared to gate-level techniques, our results indicate that selecting registers on the register-transfer level (RTL) guarantees excellent fault coverage without incurring high hardware overhead.
Keywords :
flip-flops; high level synthesis; RTL algorithm; fault coverage; flip-flop; hardware overhead; partial scan synthesis; register selection; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Feedback; Flip-flops; Hardware; Logic testing; Registers; Sequential analysis;
Conference_Titel :
Instrumentation and Measurement Technology Conference, 2002. IMTC/2002. Proceedings of the 19th IEEE
Print_ISBN :
0-7803-7218-2
DOI :
10.1109/IMTC.2002.1007105
