DocumentCode :
1669825
Title :
Area/delay driven NoC synthesis
Author :
M´zah, Abir ; Hammami, Omar
Author_Institution :
ENSTA ParisTech, Paris, France
fYear :
2011
Firstpage :
1
Lastpage :
6
Abstract :
The NoC synthesis defined as the generation of a Network On Chip (NoC) architecture optimized for a specific application subject to various constraints, is a very important step in ASIC design methodologies. In this work we will present a new NoC synthesis method based on linear programming. We will apply our algorithm on multimedia coregraphs like 263 enc MP3 dec, MPEG4 and H.264. We reduce the complexity of the problem by restricting possible connections between cores having common destination or origin edges. The obtained results give a free NoC topology which satisfies the required bandwidth and the maximum propagation delay time with an optimized area of the NoC.
Keywords :
application specific integrated circuits; integrated circuit design; linear programming; network-on-chip; 263 enc MP3 dec; ASIC design methodologies; H.264; MPEG4; NoC topology; area-delay driven NoC synthesis; common destination; linear programming; maximum propagation delay time; multimedia coregraphs; network on chip architecture; origin edges; Bandwidth; Delay; Digital audio players; MPEG 4 Standard; Propagation delay; Switches; Topology; Coregraph; Linear Programming; NoC synthesis; Optimization; complexity;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronics (ICM), 2011 International Conference on
Conference_Location :
Hammamet
Print_ISBN :
978-1-4577-2207-3
Type :
conf
DOI :
10.1109/ICM.2011.6177364
Filename :
6177364
Link To Document :
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